1. Technical Field
The present invention relates generally to data transmissions and in particular to serial data transmissions. Still more particularly, the present invention is related to an improved clock recovery system using a phase-locked loop circuit in a serial data transmission system.
2. Description of the Related Art
As serial communication speeds increased to one gigabit (Gbit) and beyond, process technologies for creating devices to meet those speeds are pushed to their limits. To compete with inherently faster technologies, alternative design techniques are required. For example, with a clock recovery circuit employing a phase-locked loop (PLL), recovery of a one Gbit data stream using traditional approaches requires all of the components of the clock recovery PLL to operate at one GHz. Generating devices operating at these frequencies can lead to lower yields of devices.
Traditionally, computers transfer data over wide, bulky, parallel cables or over slow RS232 serial buses. New technologies and the need for faster data transfers has prompted the development of a new type of serial data communication. Presently available serial technologies transfer data at much faster rates than existing parallel standards, such as small computer systems interface (SCSI). For example, SCSI data rates are presently at 20 MBaud per second. Fiber channel provides data rates of 100 MBaud per second.
To successfully provide 100 MBaud per second over a serial link with relatively slow technologies, such as complimentary metal oxide semiconductor (CMOS), new design techniques are required.
Therefore, it would be advantageous to have an improved method and apparatus for transferring serial data without requiring all components in a device to operate at the speed of the serial data stream.